Apparatus for reproducing a digital signal

ABSTRACT

A rotary head apparatus of the type which reproduces digital signals recorded in one or more oblique tracks on a recording medium, the digital signals being formatted such that one frame of the digital signals is formed of n blocks, each block having added to it a block address and a frame address, wherein the apparatus compares the frame address from the reproduced signal with a reference frame address which varies with a reference period, and the transporting speed of the recording medium is then controlled so as to make the difference between the reproduced frame address and the reference frame address constant. The apparatus does not require a conventional pilot signal servo track along the edge of the tape.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to an apparatus for reproducing digitalsignals, and more particularly an apparatus of this kind which issuitable for use in reproducing digital signals recorded on a tape byrotary heads.

2. Description of the Prior Art

There have been proposed various apparatus for recording and/orreproducing PCM coded audio and video signals in and from oblique tracksformed on a tape by rotary heads.

In general, such rotary head equipped recording and/or reproducingapparatus are provided with a tracking servo so that the rotary headscorrectly scan the recorded tracks. In the above-mentioned apparatus forrecording and/or reproducing PCM coded signals, the tracking servo usesa control signal recorded, for example, on an end portion of the tape inits width direction and a pilot signal recorded in tracks for recordingPCM-coded signals by frequency division or area division. For example,the tracking servo using the pilot signal is used in the recording andreproducing circuit for 8 mm video tape recorders and digital taperecorders equipped with rotary heads (hereinafter simply referred to as"R-DAT").

However, in using the tracking servo it is necessary to adjust with highaccuracy the position of the head in its so-called head heightdirection, i.e. perpendicular to the rotating direction of the rotaryheads, and also an angular distance between the heads, that is, aso-called angular division ratio in the case of apparatus equipped withtwo heads, thereby requiring an extremely expensive drum on which therotary heads are mounted.

Particularly in the case of the format for the R-DAT, the location ofareas in which the pilot signals for the tracking servo are recorded iscomplicated and accordingly high accuracy is required therefor.

Further, in a conventional apparatus the drum and the capstan have to beservo-controlled independently of each other so that they cannot bedriven by the same motor, resulting in a higher production cost thereof.

By way of background, the PCM signal is recorded in the followingmanner:

A plurality of blocks of PCM signals form one frame. A block address andan address of the frame to which the block belongs are added to theblocks. Next, each frame unit is interleaved and then an errorcorrecting code and so on are added to the interleaved frames. Finally,each of the frames is recorded in one or two oblique tracks formed on atape.

The PCM signal thus recorded is reproduced in a manner such that theblock data having the same frame address is sequentially written into abuffer RAM for processing PCM signals for reproduction in accordancewith the block addresses, subjected to processing such asdeinterleaving, error correction and so on, and then reproduced.

It can be noted that if several frame portions of a PCM signal can bewritten into the buffer RAM, the PCM signal can be reproduced withouthigh tracking accuracy.

Thus, there has been proposed a so-called non-tracking servo systemwhich does not rely on a tracking servo of the type which uses a controlsignal and a pilot signal as mentioned above. Such a system is disclosedin, for example, copending U.S. patent application Ser. No. 087,093,filed Aug. 19, 1987.

In this case, however, the tape transporting speed upon recording maynot be equal to that upon reproducing due to differences in variousconditions. If no correction is made, data recorded in the same trackwill be reproduced twice, the track will be jumped to reproduce data inthe next track, or the like. Thus, it is required to reproduce thesignals at the same tape speed as upon recording.

Japanese Laid-open Patent Application No. 61-39961 discloses anapparatus for controlling the tape transporting speed in response to thedifference between a write address for writing a reproduced signal froma reproduced block address into an RAM and a read address for reading awritten signal from the RAM.

However, according to the above-mentioned Japanese Laid-open PatentApplication, the frame address, which varies corresponding to rotationof the rotary heads, is not recorded on the tape so that the tapetransporting speed can not be controlled by the use of the frameaddress.

OBJECTS AND SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to propose animproved apparatus for reproducing digital signals.

It is another object of the present invention to provide an apparatusfor reproducing digital signals which does not employ a tracking servo.

It is a further object of the present invention to provide an apparatusfor reproducing digital signals which is equipped with a tapetransporting speed controller.

According to the present invention there is provided an apparatus forreproducing digital signals which have been recorded in one or moreoblique tracks on a tape by means of rotary heads, wherein one frame ofsuch digital signals is formed of a plurality of blocks of data and eachof the data blocks includes a frame address which varies with everyframe, the apparatus comprising:

(a) rotary heads for reproducing digital signals from the tape;

(b) means for transporting the tape relative to the rotary heads;

(c) deriving means for deriving the frame address from the digitalsignals reproduced by the rotary heads;

(d) generating means for generating a reference frame address whichvaries at a predetermined period;

(e) comparing means for comparing the derived frame address with thereference frame address and generating a control signal; and

(f) control means for controlling the tape speed of the tapetransporting means in response to the control signal.

These and other objects, features and advantages of the presentinvention will become apparent from the following detailed descriptionof the preferred embodiment taken in conjunction with the accompanyingdrawings, throughout which like reference numerals designate likeelements and parts.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are diagrams used for explaining a recorded data formatfor an R-DAT;

FIG. 3 is a circuit block diagram showing the whole arrangement of anembodiment of an apparatus for reproducing digital signals according tothe present invention; and

FIGS. 4A-4H, 5, 6-1, 6-2, 6-3A to C, 6-5A to C, 7, 8-1 to 11, 9-1 to 7are timing charts used for explaining various operations of theembodiment shown in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Now, an embodiment of the present invention will hereinafter bedescribed for the case where the present invention is applied to anR-DAT as an example, with reference to the accompanying drawings.

Reference is first made to the recorded data format for the R-DAT. As iscommonly known to those skilled in the art, the R-DAT has two rotaryheads angularly spaced with respect to each other by 180 , havingdifferent gap azimuth angles with respect to each other, and whichobliquely scan a tape and alternately form tracks to thereby record andreproduce PCM-coded audio signals on the tape. The tape is wrapped onthe periphery of a guiding drum by a tape wrap angle of 90°.

The two tracks formed by the respective heads, that is, a plus-azimuthtrack and a minus-azimuth track, form one frame. One frame portion ofPCM-coded data is divided into a plurality of blocks, in which a blockaddress and a frame address are recorded. In the present embodiment, itis assumed that 128 blocks of PCM-coded data are recorded in one track.

The data block is formed of 288 bits, as shown in FIG. 1. The first8-bits of data located at the top of the block is a block synchronizingsignal, the next 8-bits of data W₁ located next to the top data block isa PCM identification signal (PCM-ID), the 8-bits of data W₂ located nextto the data W₁ is the address of the block, the 8-bits of data locatednext to the block address is a parity for detecting or correcting errorswhich possibly occur in the PCM-ID and the block address, and theremaining 256 bits are the PCM data and their parity. In thisarrangement, into the lower four bits of the PCM-ID at every otherblock, there is inserted the address of the frame to which the blockbelongs. Blocks belonging to the same frame have the same frame address.

In this case, the PCM data interleave is completed by one frame, thatis, two tracks formed of plus-azimuth and minus-azimuth tracks. As shownin FIG. 2, even-numbered data L₀, L₂ . . . L₁₄₃₈ or odd-numbered dataL₁, L₃ . . . L₁₄₃₉ of the left channel and odd-numbered data R₁, R₃ . .. R₁₄₃₉ or even-numbered data R₀, R₂. . . R₁₄₃₈ of the right channel arerecorded respectively in the former and latter halves of one track. Inother words, the data are recorded over two tracks so that even if oneof the two heads is unable to reproduce signals, for example, due toclogging, the signal can be reproduced by correction or interpolation.Reference letter Q in FIG. 2 designates parity data.

The frame addresses are so added that they circulate with every 16frames.

Areas for recording a pilot signal for the tracking servo are located inthe top and end portions of each track. Generally, the tracking servocontrol is effected by the use of a reproduced pilot signal, however,such a tracking servo is not at all used in the present embodiment.

As described above, it is sufficient to write data into an RAM by theframe address and the block address to reproduce signals. Further, byvirtue of the two track interleaving, even if one of the two headscannot reproduce the data, the data can be reproduced by interpolation,so that a non-tracking servo type apparatus can reproduce signalssatisfactorily.

It is also required even for the non-tracking servo apparatus to makethe tape transporting speed during reproduction equal to the tape speedduring recording. FIG. 3 is a block diagram showing an example of aservo circuit for this purpose.

In FIG. 3, reference numeral 1 designates a rotary head which is assumedto represent two rotary heads for ease of explanation. The reproducedoutput from the rotary head 1 is supplied sequentially to a reproducedframe address detecting circuit 6 through a series connection of arotary transformer 2, a reproducing amplifier 3, a reproducing equalizercircuit 4 and a limiter 5 in this order. The reproduced frame addressdetecting circuit 6 detects the frame address contained in the lowerfour bits of the PCM-ID at every other block and supplies the same to asubtractor circuit 7.

The reproduced frame address is also utilized as a writing frame addressfor writing into the RAM memory for reproduction processing, as will bedescribed later.

A signal SWP having a frequency 16 times the frequency of a headchange-over signal RFSWP is supplied through a terminal 8 to a frequencydivider 9 to be divided by 16, thereby deriving a signal of one frameperiod. That is, the frame address is circulated by 16 frames and oneperiod of the head change-over signal RFSWP corresponds to one frame.The signal of one frame period thus produced by the frequency divider 9is supplied to a reference frame address generating circuit 10. Thereference frame address generating circuit 10 is formed of a counter forhandling four bit signals to sequentially count the signals of the frameperiod from the frequency divider 9. The counted value, that is, thereference frame address is supplied to the subtractor circuit 7. Thereference frame address from the reference frame address generatingcircuit 10 is increased by "8" in hexadecimal to be also utilized as areading frame address for reading data from the RAM for reproductionsignal processing, as will be described later.

Assuming that the tape transporting speed upon reproduction is the sameas that upon recording, the reference frame address from the referenceframe address generating circuit 10 is generated, such as 0H, 1H, 2H,EH, FH, 0H, IH ..., in hexadecimal form as shown in FIGS. 4A and 4B, atthe same timing as the generation of the head change-over signal RFSWP.The tape speed control circuit arrangement of this example controls thetape speed so as to make the reference frame address coincide with thereproduced frame address when the tape is transported at a normal speed(refer to FIG. 4C). The subtractor circuit 7 measures how much thecurrent tape transporting speed deviates from the normal tapetransporting speed. The subtraction result (FIG. 4D) thus obtained issupplied to an adder circuit 11. The adder circuit 11 adds "8" inhexadecimal to the subtraction result and supplies its output to a latchcircuit 12.

The signal SWP supplied to the terminal 8 is also supplied to a clearsignal generating circuit 13 to generate a clear pulse signal CLR (FIG.4G) for one frame period which is then supplied to the latch circuit 12as a latch signal. The latched output therefrom is supplied through aselector circuit 14 to a comparator circuit 15.

The signal SWP (FIG. 4E) is also supplied to a down counter 16 whichhandles hexadecimal signals. The down counter 16 is reset or cleared atevery frame address by the clear pulse signal CLR from the clear pulsegenerating circuit 13. Accordingly, the down counter 16 outputs thecounted values in hexadecimal as shown in FIG. 4F which are supplied tothe comparator circuit 15 as a 4-bit signal. The comparator circuit 15outputs a signal CM₁ (FIG. 4H) which goes high in level when the outputfrom the latch circuit 12 through selector 14 is smaller than thecounted value of the down counter 16 and goes low in level when theoutput from the latch circuit 12 i larger than the counted value of thedown counter 16. The output signal CM₁ from the comparator 15 issupplied through a series connection of a low pass filter 17, an addercircuit 18 and a motor drive circuit 19 to a capstan driving motor 20for controlling the tape transporting speed.

A signal FG generated by a frequency generator (not shown) arrangedcoaxially with the capstan driving motor 20 is supplied to a frequencyto voltage converting circuit 21 to derive a voltage outputcorresponding to the rotational speed of the motor 20. This voltage isfed back to the motor 20 through the adder circuit 18 and the motordrive circuit 19 to thereby servo-control the rotational speed of themotor 20.

By the circuit arrangement described above, the tape transporting speedis controlled by controlling the motor 20 as follows:

The subtractor circuit 7 detects the deviation of the tape transportingspeed from the normal tape transporting speed by detecting thedifference between frame addresses. In this case, the frame addressdifference is divided by 16, wherein "0" designates the case where thereis no difference between the frame addresses, with a scale from -1 to -8in the direction of delay and from +1 to +7 in the direction ofadvancement. A signal corresponding to the frame address difference isPWM-coded and then supplied to the capstan driving motor 20 forcontrolling the same. To be more specific, the PWM-coded output isduty-controlled such that if the frame address difference is zero, theratio of the high level period to the low level period of the PWM-codedsignal is set to 8:8, if the difference is +1, the ratio is set to 7:9,and if the difference is -1, the ratio is set to 9:7. The addition of"8" in hexadecimal by the adder circuit 11 is in preparation for theabove-mentioned duty control operation. The PWM-coding is processed bythe latch circuit 12, the comparator circuit 15 and the down counter 16.Specifically, when the output from the down counter 16 is larger thanthe output from the latch circuit 12, the comparator circuit 15 outputsthe control signal CM₁ at the high level as shown in FIG. 4H. When theoutput from the latch circuit 12 becomes larger than the output from thedown counter 16, the comparator circuit 15 outputs the control signalCMl at the low level to thereby derive the PWM-coded signal.

The relationship between the frame address difference and the PWM-codedsignal (the output from the low pass filter 17) is shown in FIG. 5.

The operations described above will now be explained with reference totiming charts shown in FIGS. 6-1 to 6-5. FIG. 6-1 indicates outputsignals reproduced by the two heads, wherein reference letter Adesignates an output signal reproduced by one of the two heads, and B anoutput signal reproduced by the other head which is angularly spaced by180° from the former and has a different azimuth angle. If the tapetransporting speed upon reproduction is made equal to that uponrecording by the speed servo control, the reference frame addressgenerated by the reference frame address generating circuit 10 iscoincident in timing with the output of the reproduced signal as shownin FIG. 6-2.

Assuming that the tape is in a normal phase, the reproduced frameaddress is expressed in hexadecimal, as shown in FIG. 6-3A. In thiscase, the control signal CM₁ from the comparator circuit 15 is, as shownin FIG. 6-3B, a signal of one frame period with a duty ratio of 50%,that is, the ratio of the high level period to the low level period is8:8. The output from the low pass filter 17 is, as shown in FIG. 6-3C, avoltage Vcc/2, where Vcc represents the power supply voltage.

Reference is next made to the case where the tape transporting speed isexcessively high so that it should be corrected to be lower, which isrepresented by FIGS. 6-4A, 4B and 4C. It is assumed, for example, thatthe reproduced frame address is advanced by 2 frame addresses ahead ofthe reference frame address 0H, as shown in FIG. 6-4A. In this case, thecontrol signal CM₁ from the comparator circuit 15 is a signal with aduty ratio of 6:10 corresponding to a frame address difference of -2 inorder to decrease the tape transporting speed with respect to a frameaddress difference of +2.

When the difference between the reproduced frame address and thereference frame address is decreased to be one frame address by thecontrol signal CM₁ at that time, the control signal CM₁ or the PWM-codedsignal PWM with a duty ratio of 7:9 corresponding to a difference of -1is derived from the comparator circuit 15. Then, the tape transportingspeed is controlled so that the control signal CM₁ becomes a PWM-codedsignal with a duty ratio of 8:8 corresponding to the coincidence of thereproduced frame address and the reference frame address. The outputfrom the low pass filter 17 is, as shown in FIG. 6-4C, a voltage signalthat is lower than Vcc/2 when the tape transporting speed is excessivelyhigh and gradually increased to Vcc/2.

Next, reference is made to the case where the tape transporting speed isexcessively low so that it should be corrected to be higher, which isrepresented by FIGS. 6-5A, 6-5B and 6-5C. It is assumed, for example,that the reproduced frame address is such that the head is positioned,as before, by two frames ahead of the reference frame address. In thiscase, the control signal CM₁ from the comparator circuit 15 becomes aPWM-coded signal corresponding to a frame address difference of +3.Then, as the frame address difference is decreased gradually, thecontrol signal CM₁ is gradually changed to PWM-coded signalscorresponding to smaller differences. Finally, the tape transportingspeed is regulated and accordingly the control signal CM₁ is set to aPWM-coded signal corresponding to the coincidence of the reproducedframe address and the reference frame address. The output from the lowpass filter 17 is gradually decreased from a voltage signal that ishigher than Vcc/2 to Vcc/2, and remains at Vcc/2 after the tapetransporting speed is regulated.

When the tape transporting speed is excessively high, the duty ratio ofthe control signal CMI from the comparator circuit 15 is changed from6:10 to 7:9 and finally to 8:8. When the output from the low pass filter17 is lower than Vcc/2, the servo is used to decrease the rotationalspeed of the motor to the normal speed.

On the other hand, when the tape transporting speed is excessively low,the duty ratio of the control signal CM₁ from the comparator circuit 15is changed from, for example, 11:5 through 10:6 to 8:8. The output fromthe low pass filter 17 is higher than Vcc/2, the servo operates toincrease the rotational speed of the motor, so that the motor isaccelerated in rotation to become the regulated speed.

The tape transporting speed is controlled as described above, so that itbecomes the normal speed when the signal indicative of the frame addressdifference outputted from the subtractor circuit 7 shows zero. Thecontrol signal CM₁ from the comparator circuit 15 is arranged so thatthe dynamic range of the servo becomes widest when the frame addressdifference becomes zero. However, in practice an offset occurs due toloads such as a cassette and so on, thereby causing a condition in whichthe servo is not locked at the time the frame address difference becomeszero as the regular point but at the time the difference is offset, forexample, by two frames.

As is apparent from FIG. 5, if the servo is locked with at a differenceof, for example, +2 frame addresses, the dynamic range in the plusdirection of the frame address difference is reduced, and accordinglythe whole dynamic range is also restricted thereby.

The reproduced frame address is also utilized as the write address forwriting data into the buffer RAM for reproduction processing, and thereference frame address as the read address for reading data from thebuffer RAM, respectively, as mentioned above.

To be specific, the RAM for reproduction processing has 16 frame memoryareas FMA1-FMA16 so as to store 16 frame portions of data therein, asshown in FIG. 7. One of the 16 frame memory areas is specified by theframe address. In this example, writing reproduced data into the RAM andprocesses such as reading the written reproduced data from the RAM,error correction and decoding thereof or the like are carried out inparallel, thereby efficiently operating the memory and reducing the timerequired for the decoding process during reproduction. This technique,however, does not directly relate to the present invention so that adetailed explanation thereof will be omitted (refer to U.S. patentapplication Ser. No. 019,583, filed Feb. 27, 1987).

For carrying out the writing and reading in parallel, as mentionedabove, by locating the frame memory areas for writing and for readingmost remotely from each other, these areas for the writing and readingwill never be superimposed on each other even if the write addressand/or read address is varied due to some reason. It is thereforepossible to accomplish the reading and writing operations easily andwithout difficulty. In other words, the margin of the memory becomeslarge.

Assuming that the servo is always locked at the time the frame addressdifference is zero, that is, without any offset, the above object can beachieved, for example, by adding the fixed value "8H" ("8" inhexadecimal) to the reference frame address, as shown in FIG. 3.However, the presence of such an offset as described above reduces themargin of the memory. If the offset is constant, it is possible to copewith the offset by adding a fixed value to the reference frame address.However, the offset varies in dependence on the amount of the load orthe like so that the mere addition of a fixed value cannot completelyfollow the varying offset value.

Thus, the embodiment of the apparatus according to the invention shownin FIG. 3 is operative to remove the offset and positively lock theservo at the time the signal indicative of the frame address differenceoutputted from the subtractor circuit 7 shows zero.

This event will now be explained in detail, referring again to FIG. 3.The output from the latch circuit 12 is supplied to one input terminalof a comparator circuit 31. The other input terminal of the comparatorcircuit 31 is fed with a value "8H" in hexadecimal. Therefore, thecomparator circuit 31 measures how far the signal indicative of theframe address difference outputted from the latch circuit 12 is offsetfrom zero. Then, the output from the comparator circuit 31 is suppliedto a selector 32 as a selection signal. The output from the selector 32is supplied to a latch circuit 33. The output from the latch circuit 33is supplied to an adder circuit 34 wherein +1 is added thereto. Theadded output from the adder circuit 34 is supplied to an input terminalof the selector 32. The output from the latch circuit 34 is alsosupplied to a subtractor circuit 35 to be decremented or subtracted byone. The output from the subtractor circuit 35 is supplied to the otherinput terminal of the selector 32. The latch circuit 33 operates when itreceives the pulse CLR from the clear signal generating circuit 13. Theselector 32 is operative to select the output from the adder circuit 34when the comparator circuit 31 detects that the output from the latchcircuit 12 is larger than "8H" and the output from the subtractorcircuit 35 when the comparator circuit 31 detects that the output fromthe latch circuit 12 is smaller than "8H". The output from the selector32 is supplied to a comparator circuit 37 through a selector 36. Thecomparator circuit 37 is also supplied with a signal from a down counter38 which handles 4-bit signals, similar to the down counter 16. The downcounter 38 is supplied with the signal SWP at its clock terminal andreset at every frame by the clear pulse CLR in the same manner as thedown counter 16. Therefore, the comparator circuit 37 derives a signalCM₂ that is PCM-coded corresponding to the output value of the selector32 and supplies the same to the motor 20 by way of a low pass filter 39,the adder circuit 18 and the drive amplifier 19, in the same manner asthe output from the aforementioned comparator circuit 15.

By the circuit arrangement as described above, even if the speed controlservo is locked in a condition that the output from the subtractorcircuit 7 contains an offset, the offset is compensated for by theoutput CM2 from the comparator circuit 37, so that the offset can beremoved from the output from the subtractor circuit 7, that is, theoutput CM₁ from the comparator circuit 15.

The above-mentioned operation will now be explained in detail withreference to FIGS. 8-1 to 8-11. FIG. 8-1 indicates output signalsreproduced by the two heads, and FIG. 8-2 the reference frame addresses.If the control signal CM₁ from the comparator circuit 15 does notcontain any offset, it should be a signal with a duty ratio of 50%, thatis, having its high level period and low level period in the ratio of8:8, as shown in FIG. 8-3. However, if the servo is locked in acondition that the reproduced frame address is offset by two frameaddresses from the reference address as shown in FIG. 8-4, the dutyratio of the control signal CM₁ becomes 6:10 as shown in FIG. 8-5.

If the reproduced frame address is offset in the plus direction as shownin FIG. 8-6, the circuits 31 to 39 operate so as to remove the offsetcontained in the control signal CM₁ from the comparator circuit 15 asshown in FIG. 8--8. Specifically, assume that the output CM₂ from thecomparator circuit 37 has a duty ratio of 50% or 8:8 as shown in FIG.8--8 when the control signal CM₁ from the comparator circuit 15 is a PWMsignal corresponding to a frame address difference of +2. Then, theselector 32 is changed over to select the output from the adder circuit34 at the next frame address so that the output signal CM₂ from thecomparator circuit 37 gradually deviates in the plus direction as shownin FIG. 8--8. Subsequently, the output CM₁ from the comparator circuit15 gradually deviates in the minus direction corresponding to the amountof the deviation in the plus direction of the output CM₂ from thecomparator circuit 37 until the duty ratio of the output CM₁ becomes 50%or 8:8. In other words, the offset contained in the signal CM₁ iscompensated for by the output signal CM₂ of the comparator circuit 37.Similarly, if the signal CM₁ is offset in the minus direction, thecontrol signal CM₂ gradually deviates in the minus direction, as shownin FIGS. 8-9 to 8-11, to thereby compensate for the minus offset of thesignal CM₁.

By the use of the output CM₂ of the comparator circuit 37 forcompensating for the offset of the signal CM₁, the dynamic range for thetape transporting speed control can be extended or widened. That is,since the offset is compensated for by a control system other than themain tape transporting speed control system, the main control systemitself always operates without any offset so that the frame addressdifference is zero, whereby a wide dynamic range is available.

Further, serving is always effected without using the frame addressdifference so that the difference between the reading frame address andthe writing frame address can be always fixed at "8H" and therebysignals are processed with the highest margin. Even though fluctuationsoccur due to servo errors, the signal processing can be stably carriedout.

The above description is given for servoing in the normal condition.However, the servo control system may fall into a hold condition, forexample, at a start or in case where the frame address cannot bereproduced from a certain time point, wherein the control signal CM₁from the comparator circuit 15 indicates an incorrect value. When such ahold condition appears, if the motor is used in common as the capstanmotor and the drum motor for the rotary heads, the rotational speed ofthe drum deviates greatly from the normal speed. Then, the relativespeed of the rotary heads to the tape also deviates from the normalspeed. Consequently, the phase lock loop (PLL) for generating a clockfor establishing the bit synchronization in the reproducing systembecomes out of the lock range and thereby the frame address cannot bereproduced even though the recorded area of PCM data is reproduced bythe heads. Accordingly, control of the tape transporting speed isrendered impossible. The above embodiment of the present invention isarranged so as to suppress or remove the above-mentioned defect as willshortly be explained.

As mentioned above, the servo circuit is operative to process reproducedsignals in a manner such that the write address and the read address areallocated for the RAM for the reproduction processing so as to producethe largest margin. However, it is unknown which RAM area the reproducedframe address will designate at the start, which is a disadvantage forthe tape transporting speed control. This is also taken into account bythe embodiment of the present invention shown in FIG. 3.

The reproduced frame address detecting circuit 6 derives a signal FRNG(FIG. 9-6) which goes low when reproduced frame addresses are stablydetected thereby. The signal FRNG is at a high level at the start orwhen the reproduced frame address cannot be detected. The signal FRNG issupplied to a pulse generator 41 which outputs a pulse PS when thesignal FRNG goes down from the high level as shown in FIG. 9-7. In otherwords, the pulse PS is derived when the reproduced frame address can bestably detected and then it is supplied to one input terminal of an ANDgate 42. The AND gate 42 is supplied at the other input terminal thereofwith a start signal ST (FIG. 9-1) through a terminal 43. Therefore, theAND gate 42 delivers the output pulse PS when the signal FRNG goes tothe low level and the reproduced frame address can be stably detectedwhen the start signal ST goes to the high level to thereby start thereproduction. The output pulse PS is supplied to the load terminal ofthe counter forming the reference frame address generating circuit 10.The reference frame address generating circuit 10 is also supplied atits preset terminal with the reproduced frame address data (FIG. 9-3)from the reproduced frame address detecting circuit 6. Thus, the countvalue of the counter forming the reference frame address generatingcircuit 10 is preset to a reproduced frame address value at the time thereproduced frame address can be stably derived (refer to FIG. 9-2). Itis therefore possible to suppress fluctuations in the servo operationand thereby set the apparatus into the operating condition in a shorttime period.

The signal FRNG from the reproduced frame address detecting circuit 6 isfurther supplied to the selectors 14 and 36 as their selection controlsignal. In the normal condition, that is, when the signal FRNG is at thelow level, the selector 14 selects the output from the latch circuit 12and the selector 36 selects the output from the selector 32.

These selectors 14 and 36 are respectively supplied at their other inputterminals thereof with the hexadecimal value "8H". Thus, at the start orwhen the reproduced frame address cannot be detected, that is, when thesignal FRNG is at the high level, the selectors 14 and 36 respectivelyoutput a digital signal indicative of "8H" in hexadecimal. Accordingly,the comparator circuits 15 and 37 respectively deliver the signals CM₁and CM₂, each with a duty ratio of 50%, to the motor 20 through the lowpass filters 17 and 39.

In the above described manner, at the start or when the reproduced frameaddress cannot be detected, the output signals CM₁ and CM₂ respectivelyfrom the comparator circuits 15 and 37 are chosen to be a referencesignal with a duty ratio of 50%, or 8:8 whereby the above-mentionedservo system is inoperative until the tape transporting speed becomesstable. Thereafter, when the reproduced frame address is stably detectedand the signal FRNG goes to the low level, the aforementioned servocircuit operates to immediately enable the reproduction mode. Thus,unlike the case where the servo circuit is connected to the motor evenat the start or when the reproduced frame address cannot be detected,the circuit arrangement according to the present invention can removedefective conditions such as when the rotational speed of the motorvaries largely, bad circulation occurs, and consequently theunreproduceable condition continues for a long time, so thatreproduction can be immediately started.

Whilst the above embodiment has been described in relation to an R-DATby way of example, the present invention can be applied to all apparatuswhich reproduce PCM signals from a recording medium on which frameaddress signals together with block address signals, which are added toblock data, are recorded at a unit of one track or a plurality oftracks.

The above description is given for a single preferred embodiment of theinvention but it will be apparent that many modifications and variationscould be effected by one skilled in the art without departing from thespirit or scope of the novel concepts of the invention so that the scopeof the invention should be determined by the appended claims only.

We claim as our invention
 1. Apparatus for reproducing digital signalswhich are recorded in one or more oblique tracks on a tape by rotaryheads, the digital signals being formatted so that one frame is formedof a plurality of data blocks, each data block including a frame addresswhich varies with every frame, said apparatus comprising:(a) rotaryheads for reproducing digital signals from the tape; (b) means fortransporting the tape relative to the rotary heads; (c) deriving meansfor deriving the frame address from the digital signals reproduced bythe rotary heads; (d) generating means for generating a reference frameaddress which varies at a predetermined period; (e) comparing means forcomparing the derived frame address with the reference frame address andgenerating a control signal; and (f) control means for controlling thetape speed of the tape transporting means in response to the controlsignal.
 2. Apparatus for reproducing digital signals according to claim1, wherein the generating means adds a predetermined offset to thereference frame address and further comprising offset reducing means forreducing said offset by comparing the output signal from said comparingmeans with a reference value and biasing said control means in responseto the comparison result.
 3. Apparatus for reproducing digital signalsaccording to claim 1, wherein said deriving means comprises detectionsignal generating means for generating a detection signal indicatingthat a frame address is not detected, and wherein said comparing meansis responsive to said detection signal to set said control signal to apredetermined value when the frame address is not detected.
 4. Apparatusfor reproducing digital signals according to claim 1 further comprisingpreset means for presetting the reproduced frame address to saidreference frame address when said apparatus is started.
 5. Apparatus forreproducing digital signals according to claim 3 further comprisingpreset means for presetting the reproduced frame address to saidreference frame address when a frame address is first detected after thecondition that the frame address could not be detected.